Cryogenic memory systems



May 19, 1964 H. F. HEATH, JR

CRYOGENIC MEMORY SYSTEMS 9 Sheets-Sheet 1 Filed June 24, 1958 IR 2 R1 IPM Q T q I l H A 1 T F 4 l Q T M M w Fif v m K 0 1 W 1 u A m M rilaiiilL7 FIG. 2

INVENTOR. HAROLD F. HEATH JR w ww COMPARE CIRCUIT A ATTORNEY May 19, 1964 H. F. HEATH, JR

CRYOGENIC MEMORY SYSTEMS 9 Sheets-Sheet 6 Filed June 24, 1958 May 19,1964 Filed June 24, 1958 H. F. HEATH, JR

CRYOGENIC MEMORY SYSTEMS 9 Sheets-Sheet 7 FIGJOD y 9, 1964 H. 'F. HEATH,JR 3,134,095

CRYOGENIC MEMORY SYSTEMS Filed June 24,- 1958 9 Sheets-Sheet 8 CE CE CET0 6 INPUT 0F Row COMPARE TRIGGER FIG. I2

COHPAREARGO A 54 Row COMPARE 72 I TRIGGER T- G RESET 2 156 K55 CB CB CBK19 K19 KI9 we 76 he 0 3 FIG. 13

l I I CD CD CD T0 G INPUT "GF Row COMPARE TRIGGER FIG. 14

May 19, 1964 Filed June 24, 1958 H. F. HEATH, JR

CRYOGENIC MEMORY SYSTEMS 9 Sheets-Sheet 9 I60 I54 no I FIG. 15 I GoNPARERESET GGIIPARE A B C F- 1 CF-2 CF-3 222; 96 98 -96 E98 96 98 ow CGoNPARE TRIGGER T- DI i To GoNRARE To OUTPUT GATEG To READ OUT GIRGuITsFOR FOR Row B ENABLE GGILs NEXT ROW GGNPARE TRIGGER IN Row A GGIIPAREREAD A 0 154 RESET 200\. 0U]- 2 To Row A READ ouT ENABLE COlLS TA G 1 T0ROW B REGISTER READ OUT ENABLE GGILs To Row G READ BUT I ENABLE msREGIsTER GGIIPARE TRIGGER j Fl TO READ WORD REGISTER United StatesPatent Ofifice 3,134,095 Patented May 19, 1964 3,134,095 CRYOGENICMEMORY SYSTEMS Harold F. Heath, lira, Poughkeepsie, N.Y., assignor toInternational Business Machines Corporation, New York, N.Y., acorporation of New York Filed June 24, 1958, Ser. No. 744,157 12 Claims.(Cl. 340-173.1)

The present invention relates to cryogenic circuits and systems and,more particularly, to improved cryogenic memory systems and novelcomparison and read out circuits usable in such systems.

An article by D. A. Buck entitled The Cryotron A SuperconductiveComputer Element, which appeared in the April 1956 issue of theProceedings of the IRE at pages 482493, includes a summary both of thetheory of superconductivity and the history of its development, andcites a number of informative publications on the subject. This articleis directed, in the main, to a discussion of superconductive circuitssuch as might be used in computer applications and proposes as a basicswitching or gating element for such circuits a device termed a cryotronwhich comprises a gate conductor of a superconductive material aroundwhich is wound a control coil. The control coil is preferably fabricatedof a superconductive material requiring a more intense magnetic field todrive it into a normal or resistive state at the operating temperatureof the circuit than is required to so drive the superconductive materialof the gate conductor. Cooling apparatus is provided for maintainingboth the gate and coil below the temperatures at which thesuperconductive materials of which they are fabricated undergotransitions between normal and superconductive states in the absence ofa magnetic field. The gating function is achieved by energizing thecontrol coil with sufficient current to render it effective to apply tothe gate conductor a magnetic field of sufiicient intensity to cause thegate conductor to assume a normal or resistive state. Devices of thistype need not be wire wound but may be also fabricated using thin films,as is illustrated in copending application Serial No. 625,512, filedNovember 30, 1956, in behalf of R. L. Garwin and assigned to theassignee of the subject application.

Another article entitled A Cryotron Catalog Memory System appeared atpages 115-119 of the Proceedings of the Eastern Joint ComputerConference, held in December 1956, which were published by the AmericanInstitute of Electrical Engineers in 1957. The catalog memory systemdescribed in this article is constructed using as storage elementscryotron trigger circuits. These trigger circuits are arranged incolumns and rows and in operation each row of the memory is used tostore the binary values of a single information word. Each of thetrigger circuits in the memory is provided with a comparison circuit andthe memory is interrogated by applying to these circuits pulsesrepresentative of a particular word. The output obtained uponinterrogation is in the form of a voltage signal which indicates whetheror not the word for which the memory is interrogated is stored in thememory.

In accordance with the principles of the subject invention, applicanthas provided improved compare circuits which may be employed in memorysystems of the above described type. Applicant has also providedimproved memory systems by employing novel interconnections between thecompare circuits which may be either the prior art type or the noveltype disclosed herein. Further, applicant has provided an improved readout circuit which may be utilized in cryogenic memory systems and whichis disclosed herein in a system which is termed a tag or associativememory. This memory consists of two registers each comprising a numberof rows of cryogenic storage devices. The first register is termed a TagRegister and each of the storage devices therein is provided with acompare circuit. The second register is a Word Register and each storagedevice therein is provided with a read out circuit. Input information isentered in the memory by storing each word of information in aparticular row of the Word Register and coincidently storing in acorresponding row of the Tag Register a tag or identifying word for theinformation word. The memory is interrogated by applying to the comparecircuits in the Tag Register pulses representative of a particular tagand, if that tag is present in the memory, an indication is obtained andthe corresponding word is read out of the Word Register. In onepreferred embodiment of an associated or tag memory disclosed herein byway of illustrating the principles of the invention, a novel comparecircuit is employed in the Tag Register and a novel read out circuit inthe Word Register. Each of these circuits are so constructed that theyalways provide at least one superconductive path under all conditions ofoperation, thereby allowing all the compare circuits to be seriesconnected with one signal source and all the read out circuits to besimilarly series connected to another signal source. Further, thecompare circuits for each row of the Tag Register are connected in alogical OR circuit which provides an output indication for that rowwhen, upon interrogation, the interrogate tag, that is, the tag forwhich the memory is interrogated, does not compare with the tag storedin that row. This type of circuit arrangement may be used with the priorart compare circuits as well as with the novel compare circuits, hereindisclosed and allows memories of either the catalog or associative typeto be constructed Without there being any limit to the number of storagepositions in each row of the memory.

Further embodiments of the invention herein disclosed show a number ofnovel compare circuits constructed in accordance with the principles ofthe invention, some of which may be connected, as above, in OR circuitsto provide the comparison indications and others of which may beconnected in AND circuits to provide the required comparisonindications. In one such embodiment, a compare circuit is provided whichoperates as a steering circuit which directs a current to one or theother of two output leads in accordance with whether or not a comparisonis obtained. This circuit is particularly adapted to use in memorysystems of the tag or associative type.

Accordingly, it is an object of the present invention to provideimproved cryogenic memory systems.

A more particular object is to provide improved catalog and/orassociative cryogenic memory systems.

A further object is to provide systems of these types wherein a largenumber of storage devices may be included in each row of the memorywithout thereby rendering the operation of the memory subject toextremely critical circuit parameters.

Still another object of the invention is to provide catalog and/ orassociative cryogenic memories which, under all conditions of operation,provide at least one superconductive path for each cirrent signalapplied thereto.

A further object is to provide novel cryogenic compare circuits and alsomemory systems using such circuits.

Another object is to provide a catalog type memory wherein the comparecircuits for each row in the memory are connected in a logical ORcircuit.

Another object is to provide an improved cryogenic compare circuit whichfunctions to steer or direct an applied current to one or the other oftwo outputs in accordance with whether or not a comparison is obtained,

as well as catalog and/ or associative memory systems using this typecompare circuit.

Still another object is to provide an improved cryogenic circuit forreading out information stored in a cryogenic memory device, as well asmemory arrays using these devices connected so that the memory may beaddressed to selectively and non-destructively read out any word storedtherein.

A further object is to provide novel catalog and/or associative memoriesincluding compare circuits wherein the compare circuits for each row areconnected in one side of a trigger circuit which indicates whether ornot a comparison is obtained when the memory is interrogated.

Still another object is to provide memories of the last described typewherein the compare circuits are connected to provide an OR circuitinput to the trigger circuits; a further object is to provide a memoryof this type wherein the compare circuits are connected to provide anAND circuit input to the trigger circuits.

Other objects of the invention will be pointed out in the followingdescription and claims and illustrated in the accompanying drawings,which disclose, by way of example, the principle of the invention andthe best mode, which has been contemplated, of applying the principle.

In the drawings:

FIG. 1 is a diagrammatic representation of a cryotron.

FIGS. 1A and 1B are block diagram representations of the cryotron ofFIG. 1.

FIG. 2 is a diagrammatic representation of an addressable cryotrontrigger circuit.

FIG. 2A is a block diagram which represents the trigger of FIG. 2without the enable inputs.

FIG. 2B is a block diagram which represents the trigger of FIG. 2 withthe enable inputs.

' FIG. 3 is a diagrammatic showing of a compare circuit constructed inaccordance with the principles of the invention.

FIG. 3A is a block diagram which represents the compare circuit of FIG.3.

' FIG. 4 is a diagrammatic showing of a further embodiment of a comparecircuit constructed in accordance with the principles of the invention.

FIG. 4A is a block diagram which represents the compare circuit of FIG.4.

FIG. 5 is a diagrammatic showing of a further embodiment of a comparecircuit constructed in accordance with the principles of the invention.

FIGS. 6 and 7 are diagrammatic representations of cryotron comparecircuits.

FIGS. 6A and 7A are block diagram representations of the comparecircuits of FIGS. 6 and 7, respectively.

FIG. 8 is a diagrammatic representation of a further embodiment of acompare circuit constructed in accordance with the principles of theinvention.

FIG. 8A is a block diagrammatic representation of the compare circuit ofFIG. 8.

FIG. 9 is a diagrammatic representation of two read out circuitsconstructed in accordance with the principles of the invention with thecircuits being connected as in one column of a memory system.

FIG. 9A is a block diagram representation of an individual read outcircuit such as is shown in FIG. 9.

FIGS. 10A, 10B, 10C and 1013, taken together, show, using block diagramrepresentations, a memory system constructed in accordance with theprinciples of the invention.

FIG. 11 shows the manner in which FIGS. 10A, 10B, 10C and 10D arearranged to form a single circuit diagram.

FIG. 12 shows the manner in which a number of compare circuits of FIG. 7are connected in a catalog and/or associative memory system constructedin accordance with the principles of the invention.

FIG. 13 is a diagrammatic showing of the manner in which a plurality ofthe compare circuits of FIG. 4 are connected in a catalog and/orassociative memory system constructed in accordance with the principlesof the invention.

FIG. 14 shows the manner in which a plurality of the compare circuitsshown in FIG. 6 are connected in a catalog and/or associative memorysystem constructed in accordance with the principles of the invention.

FIG. 15 shows the manner in which a plurality of the compare circuitsshown in FIG. 8 are connected in a catalog and/or associative memorysystem constructed in accordance with the principles of the invention.

FIG. 16 is a schematic representation of the manner in which a pluralityof the compare circuits of FIG. 8 are connected in another embodiment ofa catalog and/ or associative memoiy constructed in accordance with theprinciples of the invention.

There is shown in FIG. 1 a diagrammatic representation of a wire woundcryotron which is a gating device comprising a gate conductor 10 of asuperconductive material around which is wound a control conductor inthe form of a coil 14. In operation, the device is maintained at atemperature below that at which the superconductor material of the gateconductor undergoes transitions between normal and superconductivestates in the absence of a magnetic field. The gate conductor is, thus,normally in a superconductive state but may be driven into a normalstate by energizing the control conductor with sufficient current tocause the gate conductor to be subjected to a magnetic field which ismore intense than the critical field for the gate conductor at theoperating temperature. The control conductor is preferably fabricated ofa superconductive material having a higher critical field than that ofthe gate conductor so that it may be energized to drive the gateconductor resistive and still remain in a superconductive state. In theillustrative embodiments of the circuits of the invention shown in theother figures, the block diagram forms of FIGS. 1A or 1B are utilized torepresent cryotrons; the central block 16 represents the gate and theleads 18 and 20 the connections to the gate; one or the other of theleads 22 and 23 represents one connection to the control coil; and oneor the other of the leads 24 and 25 represents the other connection tothe control coil. The designation K with numeral designations isemployed to identify particular cryotrons in the circuits about to bedescribed. It should be noted here that, though the circuitsillustrating the principles of the invention are herein shownconstructed with wire wound cryotrons, these circuits may be constructedusing film type cryotrons of the type shown and described in copendingapplication Serial No. 625,512 filed November 30, 1956, in behalf of R.L. Garwin and assigned to the assignee of this application.

FIG. 2 shows an addressable cryotron trigger circuit of the type shownand described in the article published in the Proceedings of the EasternJoint Computer Conference which is cited above. This circuit comprises acryotron trigger with a pair of cryotrons connected in parallel with theinput cryotrons for the trigger for controlling the application ofinputs to the circuit. The trigger circuit includes six cryotrons Kl-K6which are connected in two parallel current paths between a pair ofterminals 30 and 32, the former terminal being connected to a currentsource 34 and the latter either directly to ground, as shown, or throughfurther superconductive circuits to a common or ground terminal. One ofthe parallel current paths includes the gates of cryotrons K1 and K4 andthe control coils of cryotrons K3 and K6, and the other includes thegates of cryotrons K2 and K3 and the control coils of cryotrons K4 andK5. Inputs for the circuit are applied to the control coils of cryotronsK1 and K2, inputs representative of a binary zero being applied to theformer and inputs representative of a binary one to the latter mentionedcoil. When the circuit is in the binary one state, the cryotrons K2, K3and K6 are resistive and, when in the binary zero state, the other threecryotrons are resistive, as is indicated by the l and O designations inthe blocks representing the gates of these cryotrons. When in either ofthese states, the current from source 34 is entirely in the pathincluding the superconductive cryotron gates. Cryotrons K3 and K4 may betermed cross coupling cryotrons since their coils and gates areconnected in dilierent paths so that they are efi'ective to maintain thecircuit stably in the binary zero and binary one states, respectively.The state of the circuit is manifested by the condition of the gates ofcryotrons K5 and K6, the former being resistive and the lattersuperconductive when the circuit is in the binary zero state and thecondition of each being reversed when the circuit is in the binary onestate. The cryotrons K7 and K8 are termed enable cryotrons and havetheir gates connected across the gates of input cryotrons K1 and K2,respectively. These cryotrons must be driven resistive before inputsapplied to the zero and one input lines 49 and 42, which are connectedto the coils of cryotrons K1 and K2, respectively, are efiective tochange the stable state of the circuit. The enable inputs are applied toa line 44 which is connected to the control coils for cryotrons K7 andK8 and it is only when a signal is applied to this line that the stateof the trigger circuit may be altered by applying an input signal. toone or the other of the lines 40 and 42.

The trigger circuit of FIG. 2 is, of course, usable with and without theenable cryotrons and, in the circuits shown in the other figures, thiscircuit, which is encompassed within the dotted block T in FIG. 2, isrepresented by the block diagram shown in FIG. 2A with the lines 4t) and42 representing the Zero and one input leads, the lines 46 and 48 thesupply current leads, the lines 50 the leads to the control coil of thezero output cryotron (K5 in FIG. 2), and the lines 52 the leads to thecontrol coil. of the one output cryotron (K6 in FIG. 2). Similarly, theentire addressable trigger circuit of FIG. 2 including the enablecryotrons, when shown in the latter figures, is represented by the blockdiagram AT of FIG. 2B, the portion of the circuit represented by theblock being encompassed with the dotted block labeled AT in FIG. 2. Thesame designations as are used in FIG. 2 are employed to represent thevarious input and output connections to the block diagram of FIG. 2B.

Compart Circuit A Referring now to FIG. 3, there is shown a comparisoncircuit which is hereafter to be known as compare circuit A and whichmay be utilized to interrogate the state of a trigger circuit such as isshown in FIG. 2. In FIG. 3, only the output coil leads for the triggerAT represented in block form are illustrated. The coils connected tothese leads control the state of cryotrons K? and K10, respectively,which correspond to the output cryotrons K5 and K6 shown in FIG. 2.Cryotron K9 is resistive when the trigger AT is in the zero state andcryotron K19 is resistive when the trigger is in the one state. Thecomparison circuit also includes two other cryotrons K11 and K12provided with control coils 56 and 58 to which interrogate inputsrepresentative of binary zero and binary one, respectively, are applied,and a further cryotron K13 which indicates the result of aninterrogation or comparison operation. Supply current for the circuit ofFIG. 3 is applied at a lead 61 which is connected to terminal 60 fromwhich this current may flow through one of four possible paths to aterminal 62 and lead 63 which is connected either directly or throughfurther circuitry, which is preferably superconductive, to ground. Thefirst of these paths includes the gates of cryotrons K9 and K14); thesecond includes the gates of cryotrons K11 and K12; the third includesthe gates of cryotrons K? and K12 and the control coil of cryotron K13;and the fourth path includes the gates of cryotrons K11 and K and thecontrol coil of cryotron K13. When the trigger AT is in a binary zerocondition and an interrogate input representative of one is applied,cryotrons K9 and K12 are resistive and cryotrons K11 and K14)superconductive so that the current from terminal 60 flows in the thenentirely superconductive fourth path, thereby energizing the controlcoil of cryotron K13. Similarly, when the trigger AT is storing a binaryone and an interrogate input of Zero is applied, the only completelysuperconductive path available is through the gate of cryotron K9,control coil of cryotron K13 and the gate of cryotron K12. Thus, whenthe interrogate input does not compare with the value stored in thetrigger AT, the gate or cryotron K13 is driven resistive indicating thenon-comparison. The designation 6 within the block representation forthe gate of cryotron K13 is employed to indicate that this cryotron isresistive only when the interrogate input does not compare with thevalue stored in trigger AT. When there is a comparison, either the gatesof the cryotrons K9 and K11 or the gates of the cryotrons K10 and K12are resistive so that the current divides between the first and secondpaths and the current, if any, in the coil of cryotron K13 isinsufficient to drive the gate of this cryotron resistive. This outputcryotron, therefore, remains superconductive indicating a comparisonbetween the interrogate input and the value stored in trigger AT. Incircuits shown in the figures later to be described, the block diagramCA of FIG. 3A is used to represent the portion of the compare circuitshown within the dotted box CA in FIG. 3, the designations used toidentify the control coils and the supply current leads corresponding tothose shown in FIG. 3.

Compare Circuit B Referring now to FIG. 4, there is shown anotherembodiment of a comparison circuit constructed in accordance with theprinciples of the invention. In this circuit, which is hereafterreferred to as compare circuit B, the output of the trigger AT controlsthe state of a pair of cryotrons K15 and K16, the former being resistivewhen the trigger is in a binary zero state and the latter beingresistive when the trigger is in a binary one state. The interrogateinputs are applied to control coils 70 and 72 for a pair of cryotronsK17 and K18, respectively, so that the former cryotron is resistive foran interrogate input representative of binary zero and the lattercryotron is resistive for an interrogate input representative of abinary one. The supply current for the circuit is applied to a lead 70which is connected to a terminal '71 from which the current may flowthrough one of four parallel paths to a terminal 74. The latter terminalis connected to a lead which, in turn, may be connected through furthersuperconductive circuitry (not shown) to ground. The output of thecircuit is manifested by the state of an output cryotron K19, the blockrepresentation for which includes the designation C indicating that thiscryotron is resistive when the interrogate input compares with the valuestored in the trigger AT. For example, when the trigger AT is storing abinary zero and cryotron K15 is, therefore, resistive and an interrogatepulse is applied to the coil 70 of cryotron K17 to drive that cryotronresistive, a superconductive path exists from terminal 71 through thegate of cryotron K16, the control coil of cryotron K19, and the gate ofcryotron K18 to terminal 74. Similarly, when a binary one is stored andan interrogate input representative of binary one is applied to thecontrol coil 72 of cryotron K18, the superconductive path extends fromterminal 72 through the gate of cryotron K15, the control coil ofcryotron K19, and the gate of cryotron K17 to terminal 74. The currentfiow in this path maintains the gate of cryotron K19 resistive,indicative of a comparison. When the interrogate input does not comparewith the value stored in the trigger AT, the gates of either cryotronsK16 and K17, or K15 and K18, are resistive so that the entire currentflows through the other two cryotrons and not through the coil ofcryotron K19, thereby allowing the gate of this cryotron to remain in asuperconductive state, indicative of the fact that the interrogate inputdid not compare with the value stored in the trigger. In the circuitabout to be described, the block diagram CB shown in FIG. 4A is employedto represent the portion of the compare circuit B shown in FIG. 4enclosed within the dotted box with the same designations being used ineach figure to identify the various leads for the circuit.

Compare Circuit C FIG. 5 shows a further embodiment of a compare circuitconstructed in accordance with the principles of the invention. Thiscircuit, which is termed compare circuit C, is similar to that shown inFIG. 4 and, for this reason, corresponding designations are used toindicate corresponding elements and terminals in the circuit. The onlydiiference between the circuits of FIGS. 4 and 5 is that the cryotronsK17 and K18 of FIG. 4 have been transposed in the circuit of FIG. 5 sothat the output cryotron which is again designated K19 is drivenresistive when the interrogate input does not compare with the valuestored in the trigger AT. Thus, when the interrogate input compares withthe value stored in the trigger, either cryotrons K or K17 are resistiveand cryotrons K16 and K13 superconductive, or the former cryotrons aresuperconductive and the latter resistive so that there is no current inthe control coil of cryotron K19. However, when the interrogate inputdoes not match the stored value, the only superconductive path throughthe circuit includes the control coil of K19 so that the gate of thiscryotron is in a resistive state. In the other figures about to bedescribed, the block diagram shown in FIG. 4A is also utilized torepresent the comparison circuit of FIG.

5 with the change that the diagram is designated CC instead of CB and,further, the designation 6 is used within the block employed torepresent the gate of cryotron K19 to indicate that this cryotron isresistive only when the interrogate input does not compare with thevalue stored in the trigger.

One basic and important difference between the circuits of FIGURES 4-and 5 and the circuit of FIG. 3, as well as other comparison circuitspreviously known in the art, is that in the circuits of FIGS. 4 and 5,regardless of whether or not the interrogate inputs compare or do notcompare with the value stored in the trigger, there is always acompletely superconductive path through the circuit, thereby allowing anumber of such circuits to be connected in series with the same currentsource as is demonstrated in the embodiments of the invention about tobedescribed.

Compare Circuit D The compare circuit shown in this figure correspondsto that shown in the above cited Proceedings of the East ern JointComputer Conference. In this circuit, the trigger AT controls the stateof cryotrons K21 and K22 and the interrogate inputs are applied tocontrol the state of cryotrons K23 and K24. The input current is appliedto a lead 80, which is connected to a terminal 82, and flows through atleast two of these cryotrons to a terminal 84 which is connected by alead 86 either directly or through further superconductive circuitry toground. In operation, this comparison circuit provides a path in whichcurrent may flow from terminal 82 to terminal 84 which issuperconductive when the interrogate input does not compare with thevalue stored in the trigger. When there is a comparison between theinterrogate input and the value stored in the trigger, this comparisoncircuit is resistive. The block diagram CD shown in FIG. 6A is employedin circuits later to be described to represent the compar circuit Dshown in FIG. 6.

Compare Circuit E This comparison circuit is similar to that of FIG. 6,differing only in that the position of the interrogate cryotrons K23 andK24 have been changed so that the circuit is resistive when, uponinterrogation, a non-comparison is indicated and is superconductive whena comparison is indicated. The block diagram CE shown in FIG. 7A ishereafter employed to represent the compare circuit E of FIG. 7.

Compare Circuit F This compare circuit which is shown in FIG. 8 differsfrom those previously described in that it is operable to steer a supplycurrent to one or the other of two output terminals or leads inaccordance with whether the interrogation input compares or does notcompare with the value stored in the trigger AT. This circuit includesthe gates of six cryotrons K25K3tl. One or the other of the cryotronsK25 and K26 is resistive in accordance with the value stored in thetrigger AT. Cryotrons K27 and K29 are driven resistive when a signal isapplied to a lead 99, indicative of an interrogate input representativeof binary Zero, and cryotrons K28 and K30 are driven resistive when asignal is applied to lead 92, indicative of an interrogate inputrepresentative of binary one. Supply current for the circuit is appliedto a lead 94 which is coupled to a terminal 95. The output for thecircuit is realized at one or the other of two output leads designated96 and 98 which are connected to terminals Hi0 and 102, respectively.When, upon interrogation, the interrogate input compares with the valuestored in the trigger AT, the current is steered from terminal toterminal 102 and, thus, to output lead 98; and, when the interrogateinput does not compare, the current is steered to terminal 1% and, thus,to terminal 96. In all cases, there is at least one completelysuperconductive path from the terminal 96 to either one or the other,but not both, of the terminals 96 and 9%. For example, when the triggerAT is in the one condition and, therefore, cryotron K26 is resistive andK25 superconductive, the current flows from terminal 95 through cryotronK25 to a terminal 164. From this terminal, the current will be directedthrough cryotron K27 to output terminal 102 when the interrogate inputis representative of a binary one and, therefore, a comparison isindicated, and through the cryotron K28 to terminal 190 when theinterrogate input is a binary zero and, therefore, does not compare withthe value stored in the trigger. Similarly, when the trigger AT isstoring a binary zero, the current from source 95 is directed to aterminal 106 and thence through either cryotron K29 or KSii to terminal100 or 102 in accordance with whether the interrogate input is a binaryone or a binary zero. The block diagram CF shown in FIG. 8A is employedin the circuits later to be described to represent a compare circuit Fof FIG. 8.

Read Out Circuit FIG. 9 shows two positions of a memory register whereinbinary information is stored in two addressable triggers designated AT-1and AT-2. These positions are connected in one column of an array ofcolumns and rows of memory positions. The circuitry shown associatedwith these triggers is employed to selectively read out the informationstored in the triggers AT1 and AT-2. Each of the read out circuits isshown enclosed within a dotted box designated R0. T he read out circuitR0 which is associated with trigger AT-l includes a pair of cryotronsK31 and K32, the states of which are controlled in accordance with thevalue stored in trigger AT-1. Similarly, the read out circuit associatedwith the trigger AT2 includes a pair of cryotrons K33 and K3 4, thestates of which are controlled in accordance with the value stored intrigger AT-2. Each of these read out circuits is also provided with apair of enable cryotrons which, in the read out circuit associated withtrigger AT-l, are designated K35 and K35, and, in the read out circuitassociated with trigger AT-Z, are designated K37 and 9 K38. The state ofthe cryotrons of K and K36 is controlled by enable signals which areapplied to an enable line the input lead of which is designated 110 and,similarly, the state of cryotrons K37 and K38 is controlled by enablesignals applied to an enable input designated 112. The output lead forthese enable lines are designated 111 and each of these leads may beconnected to further read out circuits which are to be enabled inresponse to signals applied to input leads 119 and 112. The read outcurrent for the circuit is applied at a lead 114 which is connected to aterminal 116, from which point the current is steered to one or theother of two output leads 118 and 120 for the particular column in whichthe triggers AT-l and AT-2 are connected. When the current from terminal116 is steered to terminal 118, it indicates that a particular one ofthe triggers in that column then being interrogated is in the binary onestate, and when current is steered to lead 120, it indicates that thetrigger being interrogated is in the binary zero state. The particularone of the triggers which is interrogated when a read out pulse isapplied to lead 114 is controlled by applied an enable signal to aselected one of the enable line 110 or 112. For example, consider thecase where trigger AT1 is in the binary zero state and it is desired tointerrogate the state of this trigger. In this case, cryotron K31 isresistive and cryotron K32 is superconductive. In order to interrogatethe trigger, it is necessary to apply an enable pulse to lead 114) andthereby drive enable cryotrons K35 and K36 resistive. No signal isapplied to enable lead 112 so that enable cryotron K37 and K38 remain ina superconductive state. When, with the cryotrons in this condition, aread out pulse is applied to lead 114, since cryotrons K31, K35 and K36are resistive, the current is directed through the then superconductivecryotron K32 to a terminal 122. The current the passes through theenable cryotron K38, which is then in a superconductive state, to outputlead 12% to indicate the binary zero condition of trigger AT1.Similarly, when the trigger AT-1 is in the binary one condition, thecurrent from terminal 116 is directed through 1 the then superconductivecryotron gate K31 to a terminal 124 and thence through enable cryotronK37 to terminal 118, indicative of the binary one stored in trigger AT1.The operation is similar when it is desired to interrogate trigger AT-2with the exception that, in this case, an enable pulse is applied tolead 112 to drive enable cryotrons K37 and K38 resistive, and no pulseis applied to enable lead 119 so that cryotrons K35 and K36 remain in asuperconductive state. Since, as in the above described interrogation,the enable cryotrons K35 and K36 provide a superconductive shunt forcryotrons K31 and K32, the current from terminal 116 is steeered to lead118 or 120 in accordance with the state of cryotrons K33 and K34 whichare controlled in accordance with the value then stored in trigger AT-2.It can be seen that any number of read out circuits for triggers such asAT1 and AT-Z may be connected in; this manner with all of the zerorepresenting cryotrons in one parallel circuit extending from terminal116 to the binary one output lead, and all of the one representingcryotrons connected in another parallel path from terminal 116 to thebinary zero output lead for the column. Each of the binary one and zerorepresenting cryotrons are provided with shunting enable cryotrons suchas are shown in FIG. 9 so that any particular one of the triggers in thecolumn may be interrogated by energizing the particular enable lead forthe read out circuit associated with that trigger and then applying aread out pulse to terminal 114.

In the circuits about to be described, the block diagram RO shown inFIG. 9A is employed to represent the read out circuits of the type shownin FIG. 9, with the designations shown in FIG. 9A corresponding to thoseused to represent the various current supply leads for the read outcircuit associated with trigger AT-l in FIG. 9.

FIGS. 10A, 10B, 10C and 10D, taken together, as indicated in FIG. 11,show a memory system which may be termed an associative or tag memory,the term being employed to indicate that each word stored in the memoryhas associated with it a tag which is also stored, and the memory isinterrogated by applying inputs representative of a particular tag tothereby read out the word associated with that tag it the tag is presentin the memory. The Tag Register is shown in FIGS. 10A and 10C, and theWord Register in FIGS. 10B and 10D. These Registers are coupled by apair of Compare Triggers which are controlled during an interrogation byTag Register Compare Circuits to cause the proper word stored in theWord Register to be read out. The Tag Register includes two rows ofaddressable memory triggers of the type shown in FIG. 2. Each of thesememory triggers is provided with a compare circuit of the type shown inFIG. 5. There are two memory triggers AT-10 and AT11 in Row A of the TagRegister and two memory triggers AT-20 and AT-21 in Row B of the TagRegister. The compare circuits are represented by the blocks CC withappended numerals corresponding to those used to identify the memorytriggers with which they are associated. The Word Register, similarly,comprises two rows of memory triggers, AT-13, AT-14 and AT-lS in Row Aand AT-23, AT-24 and AT25 in Row B. For each of the memory triggers ofthe Word Register, there is provided a read out circuit, of the typeshown in FIG. 9; the read out circuits are represented by the blockdiagram representation R0 of FIG. 9A with numerals appendedcorresponding to those employed to identify the memory triggers withwhich they are associated.

The supply current leads 46 and 48 for the memory triggers AT-1t9through AT-15 and AT20 through AT-25 are connected in series with a DC.current source which continuously supplies currents to each of thesetriggers. In a similar manner, the Row A and Row B compare triggers anda group of triggers T-2 through T5 which are employed to indicate theoutputs when the memory is interrogated have their current supply leads46 and 43 connected in series with a second DC. current source 142 whichcontinuously supplies current to these triggers. Though two sources 141)and 142 are shown, it should be noted that a single D.C. source may beutilized to provide supply current for all of the above mentionedtriggers.

Read In Operation With DC. current being supplied, information may beread into the memory by actuating one or the other of a pair of InputEnable pulse sources A and B, which sources are designated A and 150B inFIGS. 10A and 10C, and then controlling a plurality of Storage Inputpulse sources S1 through S5, there being one such source connected foreach column in the memory, so that each applies a signal representativeof either a binary one or binary zero to the addressable triggers in thecolumn to which it is connected. The Input Enable pulse source 159A isconnected to the enable inputs 44 for each of the triggers AT1tl throughAT-15 in Row A of the memory and the source 15613 is connected to theenable inputs for each of the triggers AT-Zti through AT-25 in Row B ofthe memory. Thus, for example, a tag is entered in Row A of the TagRegister by energizing source 150A and then causing input sources S1 andS2 to apply pulses representative of binary one or zero to the inputlead 42 and 40 of triggers AT-ltl and AT11. At the same time, the wordcorresponding to this tag is entered in the Word Register under thecontrol of the pulses supplied by sources S3, S4 and S5 to triggers AT-13, AT14 and AT-15, respectively. As was pointed out in the descriptionabove of these addressable triggers with particular reference to FIG. 2,their state may not be changed unless their enable inputs are energized.Thus, in the operation described above, with no pulse supplied to theenable inputs of the triggers in Row B of the memory, binary one andbinary zero pulses supplied by sources S1 through S do not affect thestate of these triggers. A tag and corresponding word may be enteredinto the triggers in Row B by causing source 159B to apply a pulse tothe enable inputs for these triggers and then causing storage inputsources S1 through S5 to apply pulses representative of the binaryvalues for the tag and word to be entered. During this input operation,no enable pulse is applied by source JlShA so that the triggers in Row Aare unaffected by the pulses supplied by sources S1 through S5.

Compare Operation Once the memory register has received its inputs asabove described, comparison operation may be undertaken. The first stepin such an operation is to cause a reset pulse source 154 to supply apulse to line 156. This line is connected to control coils for the Cinput cryotrons of the Row A and Row B compare triggers TA and TB, thecontrol coil for the one input cryotron of Register Compare Trigger T2and the control coils Zero input cryotrons of Output Triggers T3, T-4and T5. Each of the Row Compare Triggers TA and TB are similar to thetrigger shown in FIG. 2 and normally represented by the block T of FIG.2A, differing only in that the designation C is used instead of O toindicate the cryotron gates which are resistive after an interrogationwhich results in a comparison, and the designation 6 is used instead of1 for those gates which are resistive when the interrogate input doesnot compare with the values stored in the associated row of the TagRegister. Further, instead of a single binary one input cryotron, eachof these circuits is provided with a logical OR input comprising thegates of the cryotrons K19 for the compare circuits in the associatedrow, which gates are connected in series in one of the parallel paths ofthe trigger. After the reset pulse is applied, the gates of the outputcryotrons K41 and K43 of triggers TA and TB, respectively, are in aresistive state and the other output gates K42 and K44 of these gatesare in a superconductive state. Similarly, the gate of output cryotronK45 of trigger T2 is superconductive and that of cryotron K46 isresistive, indicative of the binary one state of this trigger, whereaseach of the cryotrons T3, T4 and T5 is in its binary zero representingstate.

After the reset pulse has been terminated, a pair of interrogate inputsources I1 and I2 are actuated to apply pulses to one or the other ofthe binary one or binary zero output lines connected thereto, thesepulses being representative of the interrogate input to the memory. Theinterrogate input from source 11 is applied to the proper control coils74 or 72 for the compare circuits CC- and CC-Zil in the first column ofthe Tag Register, and that from source 12 is applied to the proper onesof the control coils 70 or 72 for the compare circuits CC-ll and CC-21in the second column of the memory Tag Register. Thereafter, a first orA compare pulse is applied by a source 160 which source is connected tothe supply current input 70 for compare circuit CC-llti. The remainingcurrent supply leads for the other compare circuits are connected inseries so that the current pulse applied by source 160 is applied toeach compare circuit. This series connection is possible since, aspointed out above with respect to the compare circuits of FIG. 5, thiscompare circuit always provides at least one superconductive pathbetween leads 70 to 76, regardless of whether or not the interrogateinput compares or doesnt compare with the value stored in the memorytrigger connected to the compare circuit.

In the description above given with reference to FIG. 5, it was pointedout that the gate of the cryotron K19 in this type compare circuit isdriven resistive only when the value of the interrogate input is not thesame as the stored value. Thus, when the value of the interrogate inputfor each of the columns in a particular row of the Tag Register is thesame as the stored value, none of the output gates K19 for the comparecircuits in that row are driven resistive and, therefore, no resistanceis introduced into the then current carrying path of the associated RowCompare Trigger and that trigger remains in its reset state. Thus, forexample, if the interrogate tag compared with the tag stored in thetriggers AT-10 and ATllll, the trigger TA would not be switched, butwould remain as reset by reset source 154 with the gate of cryotron K41resistive and the gate of cryotron K42 superconductive. However, whenany one of the values of the interrogate tag fails to compare with astored value, the gate of the cryotron K19 in the corresponding comparecircuit is driven resistive, thereby switching the compare trigger forthat row. For example, if the tag for which the memory is interrogatedfails to compare with the tag stored in Row B of the Tag Register sothat either or both of the gates K19 of compare circuits CC20 and CC21are driven resistive, the Row B Compare Trigger TB is switched so thatthe gate of cryotron K44 is driven resistive and the gate of cryotronK43 is allowed to assume a superconductive state.

After one or both of the triggers T-A and T-B have been switched inaccordance with the values of the tag interrogate input, the A comparepulse applied by source 1663 is terminated and a B compare pulse issupplied by a source 170. This source supplies current to a circuit inwhich the gates of the output cryotrons of triggers TA and T-B areconnected. If the tag input fails to compare with the tag stored ineither Row A or Row B of the Tag Register and thus both of the triggersT-A and T-B are switched, the current pulse from source is directedthrough the then superconductive gates of cryotrons K41 and K43 to thebinary zero input lead 4i? for the Register Compare Trigger T2, therebyswitching this trigger to the binary zero state to indicate that the tagfor which the memory was interrogated was not present in the TagRegister. Where, however, one of the stored tags does compare, so thateither the gate of cryotron K41 or that of K43 is resistive, the currentfrom the source 170 is directed through the parallel connected gate ofeither cryotron K42 or K44, as the case may be, to enable reading out ofthe word in the Word Register which is associated with that tag. Whereboth of the stored tags compare, the current from source 170 is directedthrough the gate of cryotron K42 so that the top row only of the WordRegister is enabled for read out.

It should be pointed out that, in some memory applications, it is onlynecessary that an indication be obtained of whether or not a particularword is or is not stored in a register. The circuits of the TagRegister, together with that of the triggers TA, T-B and T2 aresufficient to accomplish this function, since, when the input word ortag fails to compare completely with any of the stored tags, theRegister Compare Trigger T2 is switched to its binary zero state,whereas, when a comparison is obtained in one of the rows, the triggerfor that row is not switched from its reset state and trigger T2 remainsin its reset or binary one state. When such an application is practiced,the gates of the compare cryotrons K42 and K44 may be shunted directlyto ground.

A further advantage of the circuit above described, wherein the novelcompare circuits utilized have their output cryotron gates connected inseries to provide an IN- CLUSIVE OR input for the Row Compare Triggers,is that the characteristics of each of the cryotrons utilized may be thesame, and the time constant of the compare trigger circuits is, in allcases, at least as brief as that of a normal six cryotron triggercircuit. This is due to the fact that, when one of the row triggers isswitched during an interrogation, the resistance of at least one of thegates of a cryotron K19 is introduced into the circuit, whereas, when areset pulse is applied, the cryotrons K19 are all in a superconductivestate so that the only resistance in the circuit is that of the crosscoupled cryotron (for example, K49 or K50 in trigger TA).

Still another advantage realized with the comparison and interrogatecircuitry thus far described is that, in all conditions of operation,there is always at least one completely superconductive path providedfor each of the current signals applied and, further, there is only onesuch superconductive path for each signal applied, with all other pathsin parallel therewith including at least one resistive cryotron gate, sothat the current signals are quickly and positively directed into thedesired paths.

Read Out Operation The pulse applied by the source 170 in the mannerdescribed above switches trigger T-2 when the interrogate tag is notpresent in any of the rows of the Tag Register. However, when there is acomparison between the interrogate tag and a particular tag stored inthe Tag Register, this pulse is steered to the output enable coils forthe memory units in the Word Register which store the word associatedwith the particular tag. For example, if the tag for which the memory isinterrogated is present in Row A, trigger T-A is switched so that thepulse supplied by source 170 is directed through the thensuperconductive gate of cryotron K42 to an enable line 190 with whichthe enable input leads of the read out circuits R043, RO-14 and RO-15 inRow A of the Word Register are connected in series. Similarly, when acomparison is realized with the tag stored in Row B of the Tag Register,the compare pulse supplied by source 170 is directed through the gate ofcryotron K41 to a terminal 193 and thence through the thensuperconductive gate of cryotron K44 to an enable drive line 194 for theread out circuits in Row B of the Word Register. Thus, when a comparisonis obtained, the Register Compare Trigger T-2 remains in the binary onecondition with the gate of cryotron K45 superconductive and the gate ofcryotron K46 resistive; and the Row Compare Trigger T-A or TB, for therow in which the comparison was obtained, is switched to a comparecondition so that the pulse from source 170 is efltective to enable theread out circuits for that row. The pulse supplied by source 170 ismaintained until the read out operation is completed.

With the circuit in this condition, a read out pulse is supplied by asource 200. This pulse is directed through the then superconductive gateK45 of Trigger T-2 to a read out line 202 for the Word Register. Line202 is connected to a terminal 2tl4 from which extend in parallel thetwo input leads 113 and 115 of read out circuit RO-13. The output leads117 and 119 are connected to the corresponding input leads 113 and 115of the other read out circuit RO-23 in the first column of the WordRegister so that the read out circuit operation is as described indetail above with reference to FIG. 9. The pulse applied to line 204appears on one or the other of the lines 117 or 119 of the read outcircuit RO-23 in accordance with the value stored in the trigger AT-13or AT23 which has been enabled for a read out operation. Where thestored value is a binary one, the pulse appears on line 117 of read outcircuit RO-23 and is applied to the binary one input lead 42 for outputtrigger T-3 to set that trigger in the binary one condition. Afterpassing through the control coil of the binary one input for triggerT-3, the read out current pulse is directed to a terminal 210. When thevalue in the trigger AT-13 or AT-23 then enabled is a binary zero, theread out pulse is directed to output line 119 of read out circuit andthence directly to terminal 219. Thus, the read out pulse is effectiveto set output trigger T-3 in the one state when the trigger AT-13 orAT-lS being interrogated is storing a binary one and the output triggerremains in the zero state when a binary zero is stored. The read outpulse is directed from terminal 210 to a terminal 212 from whence it isdirected either through the binary one input of output trigger T4 andthe binary one path through read out circuits RO24 and RO-14 to aterminal 214, or directly through the binary zero path through theseread out circuits to terminal 214 in accordance with the state of theone of the triggers AT-24 and AT-14 then enabled for read out. The readout pulse is then directed to a terminal 216 and from this terminal to agrounded terminal 218 through the proper one of the paths through readout circuits RO-15 and RO-ZS to either set trigger T-S t0 the binary onestate or allow this trigger to remain in the binary Zero state inaccordance with the value stored in the one of the triggers AT-15 orAT-25 being interrogated.

Thus, it can be seen that a single read out pulse supplied by the source200 is directed through the read out circuits for each column of theWord Register, the read out circuits for each column being connected inseries with source 200. This pulse sets the output triggers T-3, T-4 andT-S to indicate the word in the Word Register which is associated withthe tag in the Tag Register for which a comparison was indicated whenthe interrogate tag input was applied by sources I1 and 12. It should benoted that regardless of the state of the various triggers and read outcircuits, there is always one and only one completely superconductivepath from source 200 to the grounded terminal 218. Further, note shouldbe made of the fact that when, upon interrogation, no comparison isindicated in any of the rows of the Tag Register, and trigger T-2 is,therefore, switched to its binary Zero state so that the gate or"cryotron K45 is resistive and the gate of cryotron K46 issuperconductive, the read out pulse supplied by source 20 is shunteddirectly to ground through the latter gate. Further circuitry may, ofcourse, be connected between gate K46 and ground with this circuitrybeing responsive to perform one or more computer functions when the tagfor which the memory system is interrogated is not present in the TagRegister. It should also be mentioned that all of the read out circuitsneed not be serially connected with a single read out source but thesecircuits may, if desired, be connected to a number of read out currentsources.

In the above described memory system of FIGS. 10A, 10B, 10C and 10D, thecompare circuit C of FIG. 5 is used in the Tag Register. The othercompare circuits described above might also be utilized in systems ofthis type either separately in a catalog type operation where only anindication of the presence or absence of a particular wordin a memory isobtained, or in conjunction with a Word Register wherein a particularword associated with each tag is read out when an interrogate inputmatching that tag is applied to the memory system. For example, thecompare circuit CA of FIG. 3 might be substituted for that of FIG. 5 inthe register shown in FIG. 10A. In such a case, the gates of the outputcryotron K13 of the compare circuit of FIG. 3 are connected in series toprovide an OR circuit input for the row compare triggers in the samemanner as the gates of cryotron K19 are connectcd in FEGS. 10A and 10C.The only change required in the circuit of FIGS. 10A and 10C when thecompare circuit CA is employed is that, since this type compare circuitdoes not always provide a completely superconductive path, it ispreferable to utilize a separate current source for supplying thecompare A pulse for each column of the register instead of the singlesource of FIG. 10A.

The compare circuit CE of FIG. 7 might be similarly employed with thecircuit connections to the row compare triggers being made as indicatedin FIG. 12, wherein three compare circuits for one row of a Tag Registeror catalog memory are shown. Since the compare circuits CE are eithersuperconductive or resistive in accordance with whether a comparison orno comparison is obtained, it is not necessary to utilize a source suchas source 160 of FIG. 10A to supply a compare A pulse in systemsemploying the compare circuit CE. Rather, as is shown in FIG. 12, thecompare circuits themselves are connected in a series circuit in oneside of the corresponding row trigger so that, when the interrogateinputs applied are effective to drive any one of these series connectedcompare circuits resistive, the corresponding Row Compare Trigger (e.g.T-A or T-B) is switched to its no compare state.

The compare circuits CB and CD, each of which provides a resistiveindication only when the interrogate input compares with the storedvalue, may also be used in systems such as are described above. One rowof such an arrangement of the compare circuits CB shown in FIG. 4 isillustrated in FIG. 13. Here, as in FIG. A, a single source 160 isconnected in series with all of the compare circuits CB which providecompletely superconductive paths regardless of whether the interrogateinput applied does or does not compare with the value stored in theassociated storage trigger. The compare A pulse, as in the system ofFIG. 10A, controls the cryotron K19 for each compare circuit inaccordance with whether or not a comparison is obtained. However, withthe compare circuit CB, only the cryotron K19 for compare circuits inwhich a comparison is obtained are driven resistive, and the gates ofthese cryotrons are connected in parallel to provide an AND circuitrather than an OR circuit input to the corresponding Row Compare Triggerhere designated TC. With this type of arrangement, the trigger is resetby the pulse applied by source 154 to the no compare or C state and thetrigger is switched to the compare or C state when all of the gates ofthe cryotron K19 in a corresponding row of the register are drivenresistive, indicating a complete comparison. When such a comparison isobtained, the actual resistance which is inserted in the trigger circuitT-C is equal to R/n, where R is equal to the resistance of each of thecryotron gates K19 when in a resistive state, and n represents thenumber of gates connected in parallel in the AND circuit. Therefore, inorder that this relatively small resistance be sufiicient to switch thetrigger, the resistance of the gate of cross coupling cryotron K55should be approximately equal to the value R/n.

FIG. 14 illustrates the manner in which a similar system may beconstructed using the compare circuit CD shown in FIG. 6. This comparecircuit, as previously explained, is resistive only when the interrogateinput compares with the value stored in the trigger associated with thecompare circuit. The three compare circuits here shown as representativeof one row of one register are connected in parallel to provide an ANDcircuit input to the C input of the associated Compare Trigger so thatthis trigger is switched only when every compare circuit in the row isdriven resistive when the interrogate inputs are applied. Since theresistive condition is realized when the interrogate inputs are applied,there is no need, in systems employing the compare circuits CD arrangedas shown in FIG. 14, for the pulse source 160 of FIG. 13. As in thecircuit of FIG. 13, the resistance of the cross coupling cryotron in thecompare trigger should be approximately equal to the resistance of theindividual compare circuits when in a resistive state divided by thenumber of compare circuits in the row. The resistance of the individualcompare circuits is equal to R/2 where R is the resistance of theindividual cryotron gates.

The compare circuit CF shown in FIG. 8 may also be used in memorysystems of the general type shown in FIGS. 10A and 1013. This comparecircuit diifers from those previously described in that it acts as asteering circuit to direct current supplied thereto to one or the otherof two different output leads in accordance with whether or not theinterrogate input matches the value stored in the trigger associatedwith the compare circuit. FIG. 15 illustrates the manner in which thecompare circuits CF of FIG. 8 may be arranged in one row of either a TagRegister or a catalog memory system. The row shown comprises threecompare circuits CFI, CFZ, and CF3. After the interrogate inputs areapplied to these compare circuits in the manner previously described, apulse is supplied by the source 160 which pulse is directed to the inputcurrent lead 94 for the first compare circuit CF11 in the row shown. Ifthe interrogate input applied to this circuit compares with the storedvalue, this current is directed to lead 98 and from there to the inputlead 94 for the next compare circuit CF2. Similarly, if a comparison isobtained in this position, the current is directed to the output lead 98and compare circuit CFZ and thence to the input lead 94 and comparecircuit CF3. Again, if a comparison is obtained in this position, thecurrent is directed to the output lead 98 for compare circuit CF3 andthence to the input for a Row Compare Trigger T-D which is associatedwith this row of the register. This Row Compare Trigger is, in themanner described in reference to FIG. 13, reset to a no compare state bythe pulse supplied by reset source 154. The trigger is switched to thecompare state when, and only when, a comparison is obtained for each ofthe compare circuits in the row. These compare circuits, therefore,provide an AND circuit input to the Row Compare Trigger T-D. When theinterrogate input for any one of the compare circuits in the row doesnot compare with the value stored in the trigger associated with thatcompare circuit, the current pulse supplied by source is directed tooutput lead 96 for that compare circuit. The output leads 96 areconnected in a circuit which shunts the Row Compare Trigger for the rowshown and directs the current pulse from source 160 to the input leadfor the first compare circuit in the next row.

Therefore, when an interrogate input is applied to a register or memorysystem utilizing the compare circuit CF connected as shown in FIG. 15,only the Row Compare Trigger for a row in which a complete comparison isobtained is switched. Thereafter, the operation is the same as thatdescribed with reference to FIGS. 10A and 10B above wherein a B comparepulse is supplied by a source which is directed either to the lead outenable coils for a row in which a comparison has been obtained or to theRegister Compare Trigger for the Tag Register or catalog memory, as thecase may be, when the tag for which the memory is interrogated is notpresent.

When the compare circuit of FIG. 8 is employed in a Tag Register whichis associated with a Word Register as shown in FIGS. 10A, 10B, 10C and10D, the individual Row Compare Triggers may be eliminated. In thiscase, the operation is similar to that described with reference to FIG.15 with the exception that the output lead 98 for the last comparecircuit in each row is connected directly to the read out enable coilsfor the read out circuits and the Word Register in the correspondingrow. For example, considering the row shown in FIG. 15 to be the firstrow in such an array, the line 222, which in FIG. 15 is directed to thecompare input for the trigger TD, is, in the arrangement of FIG. 16,connected directly to the read out enable coils in that row of the WordRegister. When the interrogate input fails to compare with any of thetags stored in the Tag Register, the compare pulse supplied by source160 is shunted in each row until it is directed to an output lead 224which is, in turn, connected to the binary zero input 40 for theRegister Compare Trigger here designated T-6. This trigger is,therefore, set in the binary zero condition when the tag for which thememory is interrogated is not present and, when in this condition,prevents the read out pulse supplied by source 200 from being directedto the Word Register. It should be noted that in all of the embodimentsdescribed above, though only two or three positions are shown in eachrow of the register, any number of positions may be included in eachrow. Further, though in the Tag Register shown and described no read outcircuits are provided, it is of course obvious that read out circuits ofthe type shown associated with the storage triggers in the Word Registermay also be provided for the storage triggers in the Tag Register andthe read out pulse controlled to read out the information in bothregisters coincidently as in a conventional memory. When it is desiredthat the memory be capable of being interrogated in a conventionalmanner, two cryotron gates may be added to each of the read out circuitswith each of these gates connected in series with one of the enablegates, for example, gates K35 and K36 in FIG. 9. These added cryotronsmay be controlled by a conventional addressing system so that theinformation stored in any row of the memory may be read out directlymerely by energizing the proper address line and then applying a readout pulse.

It should further be noted that, though, in the illustrative embodimentsof the invention shown in the drawings and described above, onlycryotron type trigger circuits of the type shown in FIG. 2 are employedas storage devices, it should be apparent that the practice of thesubject invention is not restricted to memory systems using thisparticular type of storage device. For example, persistent currentstorage units or trigger circuits with the cross coupling cryotronsremoved might also be used as storage devices so that the states ofoutput cryotrons corresponding to cryotrons K5 and K6 are controlled inaccordance with the information value stored in the memory device.

While there have been shown and described and pointed out thefundamental novel features of the invention as applied to a preferredembodiment, it will be understood that various omissions andsubstitutions and changes in the form and details of the deviceillustrated and in its operation may be made by those skilled in the artwithout departing from the spirit of the invention. It is the intention,therefore, to be limited only as indicated by the scope of the followingclaims.

What is claimed is:

1. In a superconductor memory system; a plurality of compare circuitsarranged in bit columns and word rows; a plurality of superconductivestorage devices arranged in corresponding bit columns and word rows;each said storage device storing a bit value of an information word andeach connected to a corresponding one of said compare circuits forapplying thereto a signal representative of the bit value storedtherein; means for interrogating said memory system to determine if abit information word is stored in any word row said plurality of storagedevices comprising, means for applying interrogation signals representative of the respective bit values of said word to all therespective compare circuits in a corresponding bit column; each of saidcompare circuits being normally superconductive but being capable ofproviding a resistive output manifestation when the value stored in thestorage device to which it is connected fails to compare with the valuerepresented by the interrogation signal applied thereto; and means forindicating the result of said interrogation comprising a plurality ofoutput circuit means each associated with a respective word row of saidplurality of compare circuits and each coupled by all the comparecircuits in a respective row in series circuit relationship with respectto one another, and responsive to said resistive manifestations thereofin accordance with the INCLU- SIVE OR logical function, wherein each ofsaid compare circuits comprises first and second superconductive currentpaths connected between a first and second terminal and a third pathinterconnecting said first and second superconductive paths; said signalapplied to said compare circuit representative of the value stored inthe connected storage device and said interrogation value representingsignal applied to said compare circuit being effective to cause portionsof said paths to be driven resistive in accordance with the valuesrepresented thereby; each of said compare circuits including outputmanifestation means normally in a superconductive state but responsiveto current in said third path only to provide a resistive outputmanifestation for the circuit.

2. The circuit of claim 1 wherein said compare circuit provides at leastone superconductive path between said first and second terminalsregardless of whether said value representing signals compare or do notcompare.

3. In a memory including a plurality of storage devices each storing asingle information bit value; a plurality of read out devices eachassociated with a corresponding one of said storage devices; each ofsaid read out devices including first and second circuits; each of saidcircuits including first and second superconductive paths connected inparallel circuit relationship; each of said storage devices beingcoupled to both the first paths of the first and second circuits of acorresponding read out device and effective to apply signals thereto forcontrolling one or the other of said first paths thereof to assume aresistive state in accordance with the bit value stored in the storagedevice; further means coupled to both the second paths of said first andsecond circuits of each said read out devices for selectivelycontrolling the second paths of any particular one of said read outdevices to assume a resistive state so that each of said first andsecond circuits remain superconductive with the exception of thatparticular one path in a circuit Which was selectively controlled; aread out current source; and means connecting said current source tosaid circuits so that all first circuits are in parallel with all saidsecond circuits.

4. In a superconductor memory system; a Tag Register including aplurality of superconductor storage devices arranged in columns androws; a Word Register including a plurality of superconductor storagedevices arranged in columns and rows; input means for said memory forfirst applying signals representative of the values of a firstinformation word to said Word Register and signals repre sentative ofthe values of a first corresponding tag word to said Tag Register, andthen applying signals representative of the values of a secondinformation. word to said Word Register and signals representative ofthe values of a second corresponding tag word to said Tag Register; eachof said signals representative of a value of an information word beingapplied to the storage devices in a corresponding column of said WordRegister and each of the signals representative of a value of a tag wordbeing applied to the storage devices in a corresponding column of saidTag Register; said input means including means for controlling saidstorage devices to be responsive to said signals for causing the valuesof said first and second information words to be stored in the storagedevices in first and second rows, respectively, of said Word Registerand the values of said first and second tag words to be stored in thestorage devices in first and second corresponding rows of said TagRegister; a plurality of compare devices for the Tag Register eachcoupled to a corresponding one of the storage devices in the TagRegister and controllable thereby in accordance with the values storedtherein; a plurality of read out devices for the Word Register eachcoupled to a corresponding one of the storage devices and controllablethereby in accordance with the values stored therein; means for applyinginterrogation signals repre sentative of the values of one of said firstand second tag Words; each of said interrogation signals being appliedto the compare device coupled to the storage devices in a correspondingcolumn of said Tag Register; each of said compare devices being capableof providing an output indicative of whether the value stored in thecoupled storage device compares with the value represented by theinterrogation signal applied thereto; read out control means coupled tosaid compare devices and said read out devices; said read out controlmeans being responsive to said outputs provided by said compare devicesfor controlling the read out devices coupled to the storage devices inthe row of the Word Register corresponding to the row in the TagRegister in which the tag represented by said interrogation signals isstored; whereby an information word is read out of said Word Registerwhen interrogation signals representative of the corresponding tag wordare applied to said Tag Register.

5. The circuit of claim 4 wherein each of said compare devices isnormally superconductive and is capable of providing a resistive outputmanifestation only when the value stored in the storage device to whichit is connected does 1 9 not compare with the value represented by theinterrogation signal applied thereto.

6. The circuit of claim 5 wherein said read out control means areresponsive to the output manifestations provided by the compare devicesfor each row in the Tag Register in accordance with the INCLUSIVE ORlogical function.

7. The circuit of claim 4 wherein each of said compare devices isnormally superconductive and is capable of providing a resistive outputmanifestation only when the value stored in the storage device to whichit is connected does compare with the value represented by theinterrogation signal applied thereto.

8. The circuit of claim 4 wherein each of said compare devices comprisesat least first, second, third and fourth unique superconductive paths;and wherein, when said interrogation signals are applied, at least oneof said unique paths in the compare devices for each of the storagedevices in the Tag Register in which one of the values of said first andsecond tag words is stored remains in a superconductive state.

9. The circuit of claim 8 wherein each of said compare devices includesfirst and second terminals and said first, second, third and fourthunique superconductive paths connect said first and second terminals.

10. In a memory including a plurality of storage devices each storing asingle information bit value; a plurality of read out circuits eachcoupled to a corresponding one of said storage devices; each of saidread out circuits com prising first and second current input terminalsand first and second current output terminals and including first andsecond superconductive paths connected in parallel circuit relationshipbetween said first input terminal and said first output terminal andthird and fourth superconductive paths connected in parallel circuitrelationship between said second input terminal and said second outputterminal; each of said storage devices including means for controllingone or the other of said first and third paths of the corresponding readout circuit to become resistive in accordance with the single bit valuestored in the storage device; and means for enabling said read outcircuits comprising means coupled thereto for selectively causing saidsecond and fourth paths of particular ones thereof to become resistive.

11. In a memory system; a read out current source; first and second readout circuits connected in parallel with said source; each of said readout circuits including a plurality of series connected portions dividedinto first and second parallel paths; said circuits being maintained ata temperature at which they are normally in a superconductive state; aplurality of single bit value storage devices each associated with acorresponding one of said portions of said first read out circuit and acorresponding one of said portions of said second read out circuit; eachof said single bit value storage devices including means arranged inmagnetic field applying relationship to the first paths of thecorresponding portions of said first and second circuits for controllingone. or the other of said first paths to assume a resistive state inaccordance with the value stored in the storage device; read out enablemeansincluding means arranged in magnetic field applying relationship tothe second paths of said portions for selectively causing the secondpaths of the portions corresponding to any particular storage device toassume a resistive state; and output means for said read out circuitcomprising means responsive to current in one of said read out circuits.7

12. In a memory system; a plurality of value storage devices arranged ingroups; a plurality of read out devices each associated with acorresponding one of said storage devices; each of said read out devicesincluding first and second circuits; each of said circuits includingfirst and second parallel connected conductors; each of said conductorsbeing maintained at a temperature at which it is normallysuperconductive but responsive when a magnetic field is applied theretoto assume a resistive state; each of said storage devices includingmeans arranged in magnetic field applying relationship to said firstconductors of said first and second circuits of the corresponing readout device for causing one or the other of said first conductors toassume a resistive state in accordance with the value stored in thestorage device; read out enable means for each of said circuitscomprising means arranged in magnetic field applying relationship tosaid second conductors in said first and second circuits for selectivelycausing said second conductors to assume a resistive state; a read outcurrent source for each of said circuits; said first circuits for theread out devices associated with each group of storage devices beingconnected in series to provide a first read out current path for thatgroup of storage devices; said second circuits for the read out devicesassociated with each group of storage devices being connected in seriesto provide a second read out current path for that group of storagedevices; and output means for each group of read out devices includingmeans responsive to current in one of said read out current paths forthat group; said first and second read out current paths for each groupof read out devices being connected in parallel; said parallel connectedfirst and second read out current paths for each group being connectedin series with the parallel connected first and second current paths forthe other groups; and output means for each group of read out devicesincluding means responsive to current in one of said read out currentpaths for that group.

References Cited in the file of this patent UNITED STATES PATENTS2,691,154 Rajchman Oct. 5, 1954 2,734,187 Rajchman Feb. 7, 19562,768,367 Rajchman Oct. 23, 1956 2,832,897 Buck Apr. 29, 1958 2,837,732Nelson June 3, 1958 2,843,837 Thaler July 15, 1958 2,856,595 Selmer Oct.14, 1958 2,877,448 Nyberg Mar. 10, 1959 2,933,720 Newhouse et al. Apr.19, 1960 2,969,469 Richards Jan. 24, 1961 3,001,178 Buck Sept. 19, 1961

4. IN A SUPERCONDUCTOR MEMORY SYSTEM; A TAG REGISTER INCLUDING APLURALITY OF SUPERCONDUCTOR STORAGE DEVICES ARRANGED IN COLUMNS ANDROWS; A WORD REGISTER INCLUDING A PLURALITY OF SUPERCONDUCTOR STORAGEDEVICES ARRANGED IN COLUMNS AND ROWS; INPUT MEANS FOR SAID MEMORY FORFIRST APPLYING SIGNALS REPRESENTATIVE OF THE VALUES OF A FIRSTINFORMATION WORD TO SAID WORD REGISTER AND SIGNALS REPRESENTATIVE OF THEVALUES OF A FIRST CORRESPONDING TAG WORD TO SAID TAG REGISTER, AND THENAPPLYING SIGNALS REPRESENTATIVE OF THE VALUES OF A SECOND INFORMATIONWORD TO SAID WORD REGISTER AND SIGNALS REPRESENTATIVE OF THE VALUES OF ASECOND CORRESPONDING TAG WORD TO SAID TAG REGISTER; EACH OF SAID SIGNALSREPRESENTATIVE OF A VALUE OF AN INFORMATION WORD BEING APPLIED TO THESTORAGE DEVICES IN A CORRESPONDING COLUMN OF SAID WORD REGISTER AND EACHOF THE SIGNALS REPRESENTATIVE OF A VALUE OF A TAG WORD BEING APPLIED TOTHE STORAGE DEVICES IN A CORRESPONDING COLUMN OF SAID TAG REGISTER; SAIDINPUT MEANS INCLUDING MEANS FOR CONTROLLING SAID STORAGE DEVICES TO BERESPONSIVE TO SAID SIGNALS FOR CAUSING THE VALUES OF SAID FIRST ANDSECOND INFORMATION WORDS TO BE STORED IN THE STORAGE DEVICES IN FIRSTAND SECOND ROWS, RESPECTIVELY, OF SAID WORD REGISTER AND THE VALUES OFSAID FIRST AND SECOND TAG WORDS TO BE STORED IN THE STORAGE DEVICES INFIRST AND SECOND CORRESPONDING ROWS OF SAID TAG REGISTER; A PLURALITY OFCOMPARE DEVICES FOR THE TAG REGISTER EACH COUPLED TO A CORRESPONDING ONEOF THE STORAGE DEVICES IN THE TAG REGISTER AND CONTROLLABLE THEREBY INACCORDANCE WITH THE VALUES STORED THEREIN; A PLURALITY OF READ OUTDEVICES FOR THE WORD REGISTER EACH COUPLED TO A CORRESPONDING ONE OF THESTORAGE DEVICES AND CONTROLLABLE THEREBY IN ACCORDANCE WITH THE VALUESSTORED THEREIN; MEANS FOR APPLYING INTERROGATION SIGNALS REPRESENTATIVEOF THE VALUES OF ONE OF SAID FIRST AND SECOND TAG WORDS; EACH OF SAIDINTERROGATION SIGNALS BEING APPLIED TO THE COMPARE DEVICE COUPLED TO THESTORAGE DEVICES IN A CORRESPONDING COLUMN OF SAID TAG REGISTER; EACH OFSAID COMPARE DEVICES BEING CAPABLE OF PROVIDING AN OUTPUT INDICATIVE OFWHETHER THE VALUE STORED IN THE COUPLED STORAGE DEVICE COMPARES WITH THEVALUE REPRESENTED BY THE INTERROGATION SIGNAL APPLIED THERETO; READ OUTCONTROL MEANS COUPLED TO SAID COMPARE DEVICES AND SAID READ OUT DEVICES;SAID READ OUT CONTROL MEANS BEING RESPONSIVE TO SAID OUTPUTS PROVIDED BYSAID COMPARE DEVICES FOR CONTROLLING THE READ OUT DEVICES COUPLED TO THESTORAGE DEVICES IN THE ROW OF THE WORD REGISTER CORRESPONDING TO THE ROWIN THE TAG REGISTER IN WHICH THE TAG REPRESENTED BY SAID INTERROGATIONSIGNALS IS STORED; WHEREBY AN INFORMATION WORD IS READ OUT OF SAID WORDREGISTER WHEN INTERROGATION SIGNALS REPRESENTATIVE OF THE CORRESPONDINGTAG WORD ARE APPLIED TO SAID TAG REGISTER.